PROCESS(kongzhi)
    BEGIN
    CASE kongzhi IS
    WHEN kongzhi=>"10000000" clock:='1';sclock:='0';date:='0';set_min:='0';set_hour:='0';set_date:='0';set_nian:='0';set_yue:='0';
    WHEN kongzhi=>"01000000" clock:='0';sclock:='1';date:='0';set_min:='0';set_hour:='0';set_date:='0';set_nian:='0';set_yue:='0';
    WHEN kongzhi=>"00100000" clock:='0';sclock:='0';date:='1';set_min:='0';set_hour:='0';set_date:='0';set_nian:='0';set_yue:='0';
    WHEN kongzhi=>"00010000" clock:='0';sclock:='0';date:='0';set_min:='1';set_hour:='0';set_date:='0';set_nian:='0';set_yue:='0';
    WHEN kongzhi=>"00001000" clock:='0';sclock:='0';date:='0';set_min:='0';set_hour:='1';set_date:='0';set_nian:='0';set_yue:='0';
    WHEN kongzhi=>"00000100" clock:='0';sclock:='0';date:='0';set_min:='0';set_hour:='0';set_date:='1';set_nian:='0';set_yue:='0';
    WHEN kongzhi=>"00000010" clock:='0';sclock:='0';date:='0';set_min:='0';set_hour:='0';set_date:='0';set_nian:='1';set_yue:='0';
    WHEN kongzhi=>"00000001" clock:='0';sclock:='0';date:='0';set_min:='0';set_hour:='0';set_date:='0';set_nian:='0';set_yue:='1';
    WHEN OTHERS =>clock:='0';sclock:='0';date:='0';set_min:='0';set_hour:='0';set_date:='0';set_nian:='0';set_yue:='0';
    END CASE;
END PROCESS

其中数据定义附在下方

ENTITY  CLOCK IS
PORT(clk,clr,pause:IN STD_LOGIC;
     kongzhi:IN STD_VECTOR(7 DOWNTO 0);
     music:OUT STD_LOGIC;
     dis1,dis2,dis3,dis4,dis5,dis6,dis7,dis8:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END CLOCK;

ARCHITECTURE build OF CLOCK IS
SIGNAL nomusic,year:STD_LOGIC;
SIGNAL month:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL h1,h2,m1,m2,s1,s2:STD_LOGIC_VECTOR(3 DOWNTO 0);--时分秒
SIGNAL s11,s12,sm1,sm2,ss:STD_LOGIC_VECTOR(3 DOWNTO 0);--闹钟时分秒
SIGNAL ss1,ss2,fs,ms1,ms2:STD_LOGIC_VECTOR(3 DOWNTO 0);--秒表时分秒
SIGNAL n1,n2,n3,n4,y1,y2,d1,d2:STD_LOGIC_VECTOR(3 DOWNTO 0);--年月日
SIGNAL a,b,c,d:INTEGER range 0 to 9;
VARIABLE clock,sclock,date,set_min,set_hour,set_date,set_nian,set_yue:STD_LOGIC:='0';

谢谢各位

其中错误提示是：Error (10500): VHDL syntax error at clock.vhd(30) near text ":=";  expecting ")", or ","

如果有了解VHDL的朋友请看一下，我在线等，万分感谢

自己已经找到问题，谢谢大家